The present invention relates generally to optics, and more particularly, to bit alignment method for high data rate multi-lane data exchanging, for either inter-device or inter-system interfaces.
The present invention is related to Because of the factors like higher processing capacity of a single device, larger volume of network data throughput, and the innovations in data acquisition/waveform generation, data exchanging rate is much higher than before, that easily goes up to hundreds-Gigabit per second per device. For example, a 6 bit, 56 Gsample/second (56 GS/s) analog-to-digital converter (ADC) will generate 56 G*6 bit=336 Gb/s from a single channel.
Due to limited number of I/Os, higher interface capacity is usually achieved by increasing the data rate of each lane. The common data rate currently in use is 10.3˜13 Gb/s per lane, and looking forward to 25˜28 Gb/s. Such data rate is not possible by using the conventional source synchronous approach which requires the signals aligned to each other and latched in receiver device by a single clock. Instead, a clock/data recovery (CDR) unit is always included in the receiver interface for each lane, to recover both the clock and data signal from input data stream with provided reference clock. Serial-to-parallel converter (for transmitter) or parallel-to-serial converter (for receiver) is used to bridge the high-speed interface and lower speed processing, so such interface is also called SerDes (Serializer/Deserializer). Three factors make random delay from transmitter input to receiver output: 1) the nature of CDR causes random phase in the recovered data, which makes the data up to one UI (unit interval) earlier or later after each reset; 2) without serializer/deserializer synchronous reset, there will be bit skew up to parallel word width among different lanes; 3) PCB trace skew because of material and trace length.
When multiple high-speed SerDes lanes are used as a bundle, applications usually have data aligned among the lanes at transmitter, and require same pattern/alignment outputted from receiver. For another application, not only the bits among different lanes need to be aligned, but also that the receiver parallel data output shall be word-aligned with transmitter side. The solution to guarantee these alignments at receiver outputs is the problem that the present invention attempts to solve.
So far there are two categories of approaches available: one for packet interface such as 40 G/100 G Ethernet (IEEE 802.3ba-2010, “Amendment 4: Media Access Control Parameters, Physical Layers, and Management Parameters for 40 Gb/s and 100 Gb/s Operation”, section 82.2) and Interlaken (“Interlaken Protocol Definition”, Cortina Systems and Cisco Systems, rev. 1.2, section 5.4), and another for data stream interface such as receiver at digital-to-analog converter (DAC).
We use Interlaken as example to explain the widely used approach for packet case. There are two steps for lane alignments: first step is to find word boundary, and second step is for overall alignment. The first step is achieved by using 64B/67B encoding, through which the receiver (in particular 64B/67B decoding unit) looks for the control or flag code of the 3-bit overhead, to determine the word boundary. The second step is using synchronization pattern for overall alignment, which is identified by a special flag in the 3 bit overhead field. This solution not only guarantees bit-level alignment for all the lanes, but also achieves word-alignment with transmitter. The problem for this solution is that it requires additional overhead which increases data rate.
One solution for data stream alignment is seen in MICRAM's company confidential document, which aligns every two lanes using identical pattern. One suggested solution is using PRBS (Pseudo-Random Bit Sequence), and then to shift one lane bit-by-bit until it is aligned (no difference detected) or reaches a threshold (the maximum number of shifts). When threshold is reached, it requires tuning the other lane or reversing the tuning direction. This solution requires bit-by-bit adjustment, which is only possible using hardware implementation to achieve acceptable aligning speed. Moreover, this approach is not reliable when the signal received is not error free, for which case “unmatch” may always be encountered even when the two lanes are actually aligned.
Accordingly, there is a need for a latching WSS/WB the can be used in reconfigurable BU in submarine network, that overcomes the shortcomings of prior efforts.